SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

BERTOZZI, Davide
 Distribuzione geografica
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Continente #
NA - Nord America 18.066
AS - Asia 8.796
EU - Europa 3.820
SA - Sud America 1.334
Continente sconosciuto - Info sul continente non disponibili 328
AF - Africa 172
OC - Oceania 20
Totale 32.536
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Nazione #
US - Stati Uniti d'America 17.705
SG - Singapore 3.391
CN - Cina 2.214
BR - Brasile 1.040
VN - Vietnam 947
UA - Ucraina 775
HK - Hong Kong 703
DE - Germania 651
IT - Italia 616
TR - Turchia 523
GB - Regno Unito 425
FI - Finlandia 299
FR - Francia 261
JP - Giappone 231
RU - Federazione Russa 214
SE - Svezia 191
BD - Bangladesh 161
IN - India 157
CA - Canada 155
MX - Messico 138
PL - Polonia 129
AR - Argentina 105
IQ - Iraq 83
ID - Indonesia 70
ZA - Sudafrica 65
AT - Austria 58
EC - Ecuador 50
ES - Italia 50
PK - Pakistan 47
CO - Colombia 43
NL - Olanda 39
SA - Arabia Saudita 33
MA - Marocco 31
PH - Filippine 31
UZ - Uzbekistan 26
MY - Malesia 24
BE - Belgio 23
VE - Venezuela 22
TN - Tunisia 21
CL - Cile 20
PY - Paraguay 19
TW - Taiwan 19
JM - Giamaica 16
KE - Kenya 15
AE - Emirati Arabi Uniti 14
LT - Lituania 14
IL - Israele 13
JO - Giordania 13
OM - Oman 13
AU - Australia 12
CR - Costa Rica 12
EG - Egitto 12
RS - Serbia 12
UY - Uruguay 12
AZ - Azerbaigian 10
BO - Bolivia 10
NP - Nepal 10
PE - Perù 10
CZ - Repubblica Ceca 8
IR - Iran 7
KW - Kuwait 7
NZ - Nuova Zelanda 7
DO - Repubblica Dominicana 6
DZ - Algeria 6
ET - Etiopia 6
GT - Guatemala 6
HN - Honduras 6
AL - Albania 5
IE - Irlanda 5
KR - Corea 5
KZ - Kazakistan 5
RO - Romania 5
BY - Bielorussia 4
DK - Danimarca 4
GE - Georgia 4
HR - Croazia 4
KG - Kirghizistan 4
MD - Moldavia 4
NI - Nicaragua 4
PA - Panama 4
TH - Thailandia 4
AF - Afghanistan, Repubblica islamica di 3
BG - Bulgaria 3
CH - Svizzera 3
EE - Estonia 3
EU - Europa 3
GA - Gabon 3
GR - Grecia 3
KH - Cambogia 3
PS - Palestinian Territory 3
QA - Qatar 3
TT - Trinidad e Tobago 3
A2 - ???statistics.table.value.countryCode.A2??? 2
AM - Armenia 2
AO - Angola 2
BH - Bahrain 2
BN - Brunei Darussalam 2
BS - Bahamas 2
GY - Guiana 2
LB - Libano 2
Totale 32.172
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Città #
Singapore 2.194
Ashburn 2.133
Fairfield 1.964
Woodbridge 1.713
Houston 1.154
San Jose 888
Jacksonville 868
Seattle 792
Beijing 773
Santa Clara 767
Ann Arbor 730
Hong Kong 696
Wilmington 676
Cambridge 631
Chandler 631
Council Bluffs 464
Ho Chi Minh City 356
Izmir 320
Nanjing 268
Hanoi 240
Tokyo 227
Los Angeles 211
Princeton 197
Milan 190
Lauterbourg 167
New York 167
Munich 163
Boardman 162
Addison 160
Ferrara 160
Dallas 156
San Diego 154
Warsaw 121
Helsinki 110
Shanghai 94
São Paulo 93
Mexico City 89
Chicago 87
Shenyang 71
Nanchang 62
Toronto 57
Orem 53
Brooklyn 51
Tianjin 51
London 49
San Francisco 49
Vienna 45
Hefei 41
Montreal 41
Chennai 40
Falkenstein 40
Hebei 40
Da Nang 39
Jiaxing 39
Moscow 39
Haiphong 38
The Dalles 38
Atlanta 37
Baghdad 37
Frankfurt am Main 36
Changsha 35
Stockholm 35
Johannesburg 33
Mountain View 32
Boston 30
Turku 30
Norwalk 29
Phoenix 29
Redwood City 28
Rio de Janeiro 28
Bologna 27
Zhengzhou 26
Tashkent 25
Amsterdam 24
Indiana 24
Jakarta 24
Washington 24
Brasília 23
Brussels 22
Buffalo 22
Auburn Hills 21
Denver 21
Curitiba 20
Des Moines 20
Guangzhou 20
Jinan 20
Orange 20
Barnet 19
Belo Horizonte 19
Ningbo 19
Columbus 18
Dhaka 18
Manchester 17
Nuremberg 17
Quito 17
Rome 17
Ankara 16
Guayaquil 16
Lahore 16
New Delhi 16
Totale 22.876
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Nome #
SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine-Grained Design Space Exploration of Solid State Drives 331
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System 306
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip 284
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization 263
A network model for routing-fault-free wavelength selection in WRONoCs design 259
Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper) 256
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems 250
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems 243
PROTON+: A placement and routing tool for 3d optical networks-on-chip with a single optical layer 240
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers 238
Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive 237
Network-on-chip architectures and design methods 236
Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip Multiprocessors 236
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories 229
Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs 226
Cooperative built-in self-testing and self-diagnosis of NOC bisynchronous channels 226
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints 223
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms 222
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study 221
Analysis of reliability/performance trade-off in Solid State Drives 221
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies 219
Exploring Communication Protocols for Optical Networks-on-Chip based on Ring Topologies 219
Dyafnoc: Dynamically reconfigurable noc characterization using a simple adaptive deadlock-free routing algorithm with a low implementation cost 217
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration 216
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters 216
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain 215
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 215
Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer 214
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost 214
Ultra-low latency NoC testing via pseudo-random test pattern compaction 214
Energy-Efficient Network on Chip Design 213
The design predictability concern in optical network-on-chip design 213
Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis 212
Abstract Modelling of Switching Elements for Optical Networks-on-Chip with Technology Platform Awareness 212
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems 208
A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness 208
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline 208
Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems 208
NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators 207
Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs 207
Cost-effective and flexible asynchronous interconnect technology for GALS networks-on-chip 206
Allocation and Scheduling for MPSoCs via decomposition and no-good generation 204
State-of-the-Art SoC Communication Architectures 201
Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers 201
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings 199
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 198
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors 197
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation 197
Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip 197
Process Variation and Layout Mismatch Tolerant Design of Source Synchronous Links for GALS Networks-on-Chip 197
Bringing Network-on-Chip Links to 45nm 196
A Cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MPSoCs 196
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming 195
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart 195
Xpipes: a Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs 192
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework 191
A high-efficiency wind-flow energy harvester using micro turbine 191
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs 190
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs 190
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives 190
Power efficiency of switch architecture extensions for fault tolerant NoC design 190
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices 190
Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology 189
Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology 189
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints 189
Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip 189
Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology 188
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic 187
Control- and Data-Path Decoupling in the Design of a NoC Switch: Area, Power and Performance Implications 186
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches 186
Optimizing built-in pseudo-random self-testing for network-on-chip switches 185
A Retrospective Look at Xpipes: The Exciting Ride from a Design Experience to a Design Platform for Nanoscale Networks-on-Chip 185
Variation tolerant NoC design by means of self-calibrating links 184
Energy-Reliability Trade-Off for NoCs 182
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip 182
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. 181
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration 181
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style 180
Transparent Lifetime Built-In Self-Testing of Networks-on-Chip Through the Selective Non-Concurrent Testing of their Communication Channels 180
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms 179
Performance analysis of arbitration policies for SoC communication architectures 179
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. 179
Contrasting Multi-Synchronous MPSoC Design Styles for Fine-Grained Clock Domain Partitioning: the Full-HD Video Playback Case Study 178
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies 177
Battery Lifetime Optimization for Energy-Aware Circuits 177
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow 177
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC 176
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints 176
Design automation beyond its electronic roots: toward a synthesis mothodology for wavelength-routed optical networks-on-chip 176
Non Volatile Memory Partitioning Scheme for Technology-based Performance-Reliability Trade-off 175
Flexible DOR Routing for Virtualization of Multicore Chips 174
Designing Network On-Chip Architectures in the Nanoscale Era 173
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip 173
Efficient Implementation of Distributed Routing Algorithms for NoCs 171
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing 171
Design Space Exploration of Wavelength-Routed Optical NoC Topologies for 3D-Stacked Multi- and Many-Core Processors. 170
Network Interface Architecture and Design Issues 169
Power aware network interface management for streaming multimedia 168
Network-on-chip architectures and design methods 168
Guided participatory research on parallel computer architectures for k-12 students through a narrative approach 167
Totale 20.301
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Categoria #
all - tutte 147.875
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 15.853
Totale 163.728
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.961 0 204 206 21 75 118 118 96 59 161 245 658
2022/20231.732 202 21 49 205 263 249 161 177 225 16 100 64
2023/2024776 90 116 49 26 59 77 40 60 5 22 17 215
2024/20253.707 104 104 345 91 479 497 78 166 477 457 575 334
2025/202611.401 1.079 591 941 1.346 1.812 623 1.287 603 1.205 1.306 390 218
2026/2027972 317 655 0 0 0 0 0 0 0 0 0 0
Totale 32.536