SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

BERTOZZI, Davide
 Distribuzione geografica
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Continente #
NA - Nord America 15.117
AS - Asia 6.135
EU - Europa 3.316
SA - Sud America 1.064
AF - Africa 99
OC - Oceania 13
Continente sconosciuto - Info sul continente non disponibili 5
Totale 25.749
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Nazione #
US - Stati Uniti d'America 14.904
SG - Singapore 2.482
CN - Cina 1.856
BR - Brasile 900
UA - Ucraina 764
HK - Hong Kong 648
DE - Germania 624
IT - Italia 490
TR - Turchia 485
GB - Regno Unito 379
VN - Vietnam 310
FI - Finlandia 287
RU - Federazione Russa 202
SE - Svezia 184
PL - Polonia 123
MX - Messico 114
CA - Canada 80
IN - India 70
FR - Francia 68
AR - Argentina 66
AT - Austria 56
ID - Indonesia 48
ZA - Sudafrica 47
BD - Bangladesh 45
IQ - Iraq 36
ES - Italia 35
EC - Ecuador 33
JP - Giappone 27
NL - Olanda 27
BE - Belgio 22
MA - Marocco 18
CO - Colombia 16
PY - Paraguay 16
PK - Pakistan 15
TW - Taiwan 12
LT - Lituania 11
CL - Cile 10
TN - Tunisia 10
IL - Israele 9
UZ - Uzbekistan 9
AU - Australia 8
KE - Kenya 8
SA - Arabia Saudita 8
VE - Venezuela 8
AZ - Azerbaigian 7
PE - Perù 7
RS - Serbia 7
AE - Emirati Arabi Uniti 6
CZ - Repubblica Ceca 6
IR - Iran 6
JO - Giordania 6
DZ - Algeria 5
EG - Egitto 5
HN - Honduras 5
KW - Kuwait 5
PH - Filippine 5
UY - Uruguay 5
DK - Danimarca 4
DO - Repubblica Dominicana 4
KZ - Kazakistan 4
MY - Malesia 4
NP - Nepal 4
NZ - Nuova Zelanda 4
OM - Oman 4
RO - Romania 4
AF - Afghanistan, Repubblica islamica di 3
AL - Albania 3
EE - Estonia 3
ET - Etiopia 3
EU - Europa 3
GE - Georgia 3
KR - Corea 3
A2 - ???statistics.table.value.countryCode.A2??? 2
BG - Bulgaria 2
BH - Bahrain 2
BY - Bielorussia 2
CH - Svizzera 2
CR - Costa Rica 2
GR - Grecia 2
GY - Guiana 2
HR - Croazia 2
KG - Kirghizistan 2
KH - Cambogia 2
LB - Libano 2
LU - Lussemburgo 2
NO - Norvegia 2
AM - Armenia 1
AO - Angola 1
BB - Barbados 1
BM - Bermuda 1
BO - Bolivia 1
CI - Costa d'Avorio 1
HT - Haiti 1
IE - Irlanda 1
JM - Giamaica 1
LA - Repubblica Popolare Democratica del Laos 1
NI - Nicaragua 1
NR - Nauru 1
PA - Panama 1
PS - Palestinian Territory 1
Totale 25.740
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Città #
Fairfield 1.964
Woodbridge 1.713
Ashburn 1.497
Singapore 1.446
Houston 1.141
Jacksonville 866
Seattle 790
Ann Arbor 730
Beijing 706
Santa Clara 703
Wilmington 675
Hong Kong 646
Cambridge 631
Chandler 631
Izmir 319
Nanjing 268
Princeton 197
Milan 172
Los Angeles 166
Munich 163
Addison 160
Boardman 160
San Diego 151
Ferrara 146
Dallas 135
Ho Chi Minh City 135
Warsaw 118
New York 102
Helsinki 99
Shanghai 91
Mexico City 82
São Paulo 78
Chicago 76
Shenyang 71
Hanoi 69
Nanchang 62
Tianjin 49
Vienna 44
Hefei 41
London 41
Falkenstein 40
Hebei 40
Jiaxing 39
Brooklyn 38
Moscow 38
The Dalles 35
San Francisco 34
Changsha 33
Mountain View 32
Stockholm 32
Montreal 31
Boston 30
Turku 30
Norwalk 29
Chennai 27
Redwood City 27
Tokyo 26
Johannesburg 25
Rio de Janeiro 25
Indiana 24
Zhengzhou 24
Brasília 23
Frankfurt am Main 22
Auburn Hills 21
Brussels 21
Toronto 21
Atlanta 20
Des Moines 20
Jinan 20
Orange 20
Ningbo 19
Washington 19
Council Bluffs 18
Guangzhou 18
Jakarta 18
Bologna 17
Curitiba 17
Phoenix 17
Belo Horizonte 16
San Mateo 16
Amsterdam 15
Baghdad 15
Columbus 15
Denver 15
Falls Church 15
Salt Lake City 15
Salvador 15
Tappahannock 15
Verona 14
Ankara 13
Da Nang 13
Dhaka 13
Nuremberg 13
Orem 13
Kunming 11
Pittsburgh 11
Hangzhou 10
Poplar 10
Quito 10
Sorocaba 10
Totale 18.617
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Nome #
SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine-Grained Design Space Exploration of Solid State Drives 250
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip 239
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System 223
Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper) 216
Network-on-chip architectures and design methods 210
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems 208
A network model for routing-fault-free wavelength selection in WRONoCs design 206
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems 199
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories 194
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization 194
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms 190
Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip Multiprocessors 190
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters 189
Cooperative built-in self-testing and self-diagnosis of NOC bisynchronous channels 188
Ultra-low latency NoC testing via pseudo-random test pattern compaction 188
Energy-Efficient Network on Chip Design 187
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints 187
Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive 187
Exploring Communication Protocols for Optical Networks-on-Chip based on Ring Topologies 185
Analysis of reliability/performance trade-off in Solid State Drives 182
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers 180
Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs 179
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies 179
Dyafnoc: Dynamically reconfigurable noc characterization using a simple adaptive deadlock-free routing algorithm with a low implementation cost 179
NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators 178
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost 177
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 176
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain 175
Process Variation and Layout Mismatch Tolerant Design of Source Synchronous Links for GALS Networks-on-Chip 175
Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis 172
Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs 172
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework 171
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study 171
The design predictability concern in optical network-on-chip design 170
A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness 170
Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems 170
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems 168
Abstract Modelling of Switching Elements for Optical Networks-on-Chip with Technology Platform Awareness 168
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline 168
PROTON+: A placement and routing tool for 3d optical networks-on-chip with a single optical layer 168
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming 166
State-of-the-Art SoC Communication Architectures 166
Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology 166
Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers 166
Allocation and Scheduling for MPSoCs via decomposition and no-good generation 165
Bringing Network-on-Chip Links to 45nm 165
Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology 165
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors 165
Xpipes: a Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs 165
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration 165
Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology 164
Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer 163
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation 163
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs 162
Optimizing built-in pseudo-random self-testing for network-on-chip switches 162
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 161
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart 161
A Cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MPSoCs 160
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches 159
Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip 158
Cost-effective and flexible asynchronous interconnect technology for GALS networks-on-chip 157
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints 155
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip 154
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives 154
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs 153
Variation tolerant NoC design by means of self-calibrating links 153
Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip 153
Designing Network On-Chip Architectures in the Nanoscale Era 152
A high-efficiency wind-flow energy harvester using micro turbine 152
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms 151
Performance analysis of arbitration policies for SoC communication architectures 151
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC 150
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. 150
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings 150
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies 149
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip 149
Power efficiency of switch architecture extensions for fault tolerant NoC design 149
Energy-Reliability Trade-Off for NoCs 148
Flexible DOR Routing for Virtualization of Multicore Chips 147
A Retrospective Look at Xpipes: The Exciting Ride from a Design Experience to a Design Platform for Nanoscale Networks-on-Chip 147
Non Volatile Memory Partitioning Scheme for Technology-based Performance-Reliability Trade-off 145
Network Interface Sharing Techniques for Area Optimized NoC Architectures 145
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic 145
Transparent Lifetime Built-In Self-Testing of Networks-on-Chip Through the Selective Non-Concurrent Testing of their Communication Channels 145
Control- and Data-Path Decoupling in the Design of a NoC Switch: Area, Power and Performance Implications 144
Battery Lifetime Optimization for Energy-Aware Circuits 144
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms 144
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints 144
Efficient Implementation of Distributed Routing Algorithms for NoCs 143
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. 143
Contrasting Multi-Synchronous MPSoC Design Styles for Fine-Grained Clock Domain Partitioning: the Full-HD Video Playback Case Study 143
Application-specific power-aware workload allocation for voltage scalable MPSoC platforms 142
Spice-Accurate SystemC Macromodels of Noisy On-Chip Communication Channels 142
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style 141
Power aware network interface management for streaming multimedia 141
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration 141
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices 140
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing 139
Network-on-chip architectures and design methods 138
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design 138
Totale 16.616
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Categoria #
all - tutte 123.536
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 13.244
Totale 136.780
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.570 0 0 0 0 0 364 105 337 58 356 227 123
2021/20222.065 104 204 206 21 75 118 118 96 59 161 245 658
2022/20231.732 202 21 49 205 263 249 161 177 225 16 100 64
2023/2024776 90 116 49 26 59 77 40 60 5 22 17 215
2024/20253.707 104 104 345 91 479 497 78 166 477 457 575 334
2025/20265.894 1.079 591 941 1.346 1.812 125 0 0 0 0 0 0
Totale 26.057