SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

BERTOZZI, Davide
 Distribuzione geografica
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Continente #
NA - Nord America 12.713
EU - Europa 2.415
AS - Asia 2.127
SA - Sud America 16
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 5
AF - Africa 1
Totale 17.288
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Nazione #
US - Stati Uniti d'America 12.702
CN - Cina 1.116
UA - Ucraina 739
SG - Singapore 495
TR - Turchia 464
IT - Italia 419
DE - Germania 382
GB - Regno Unito 305
FI - Finlandia 185
SE - Svezia 155
PL - Polonia 82
AT - Austria 50
FR - Francia 32
BE - Belgio 22
ID - Indonesia 19
RU - Federazione Russa 16
BR - Brasile 13
CA - Canada 11
IN - India 11
ES - Italia 9
AU - Australia 8
IR - Iran 5
NL - Olanda 5
TW - Taiwan 5
EU - Europa 3
MY - Malesia 3
NZ - Nuova Zelanda 3
A2 - ???statistics.table.value.countryCode.A2??? 2
AR - Argentina 2
BG - Bulgaria 2
CZ - Repubblica Ceca 2
HK - Hong Kong 2
JP - Giappone 2
KR - Corea 2
LU - Lussemburgo 2
RO - Romania 2
AL - Albania 1
BD - Bangladesh 1
CH - Svizzera 1
CO - Colombia 1
DK - Danimarca 1
DZ - Algeria 1
EE - Estonia 1
IQ - Iraq 1
NO - Norvegia 1
PK - Pakistan 1
RS - Serbia 1
Totale 17.288
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Città #
Fairfield 1.964
Woodbridge 1.713
Houston 1.132
Ashburn 935
Jacksonville 866
Seattle 779
Ann Arbor 730
Wilmington 668
Cambridge 631
Chandler 631
Santa Clara 424
Singapore 384
Izmir 318
Beijing 299
Nanjing 267
Princeton 197
Milan 167
Addison 160
Boardman 160
San Diego 151
Ferrara 131
Shanghai 89
Warsaw 82
Shenyang 71
Nanchang 62
Los Angeles 49
Vienna 41
Hebei 40
Jiaxing 39
Tianjin 35
Changsha 32
Mountain View 32
Munich 31
Helsinki 29
Norwalk 29
Redwood City 27
Indiana 24
Zhengzhou 23
London 22
Auburn Hills 21
Brussels 21
Orange 20
Jinan 19
Ningbo 19
New York 18
Des Moines 17
Washington 17
Jakarta 16
San Mateo 16
Falls Church 15
Tappahannock 15
Chicago 11
Guangzhou 11
Kunming 11
Bologna 10
Taizhou 9
Hangzhou 8
Kilburn 8
Verona 8
Dearborn 7
San Francisco 7
Toronto 7
Paris 6
Changchun 5
Lanzhou 5
Philadelphia 5
Yellow Springs 5
Bremen 4
Chiswick 4
Frankfurt am Main 4
Hounslow 4
Lappeenranta 4
Melbourne 4
Redmond 4
Taipei 4
Florence 3
Kuala Lumpur 3
New Bedfont 3
Nuremberg 3
Ottawa 3
Pavullo Nel Frignano 3
Pensacola 3
Settimo Milanese 3
Stockholm 3
Walnut 3
Andover 2
Ardabil 2
Brno 2
Buffalo 2
Castellón 2
Columbia 2
Düsseldorf 2
Florianópolis 2
Haikou 2
Höst 2
Jinhua 2
Karlsruhe 2
Madrid 2
Manchester 2
Padova 2
Totale 13.893
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Nome #
SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine-Grained Design Space Exploration of Solid State Drives 186
Network-on-chip architectures and design methods 162
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System 155
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip 154
Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper) 151
A network model for routing-fault-free wavelength selection in WRONoCs design 146
Energy-Efficient Network on Chip Design 142
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems 142
Ultra-low latency NoC testing via pseudo-random test pattern compaction 139
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems 138
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters 138
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms 130
Dyafnoc: Dynamically reconfigurable noc characterization using a simple adaptive deadlock-free routing algorithm with a low implementation cost 130
Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs 128
Xpipes: a Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs 128
Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip Multiprocessors 128
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories 127
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers 127
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints 126
Cooperative built-in self-testing and self-diagnosis of NOC bisynchronous channels 126
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization 126
Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis 125
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC 122
Performance analysis of arbitration policies for SoC communication architectures 122
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration 122
Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive 122
Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology 121
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study 121
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems 120
State-of-the-Art SoC Communication Architectures 119
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies 119
Allocation and Scheduling for MPSoCs via decomposition and no-good generation 118
A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness 118
Exploring Communication Protocols for Optical Networks-on-Chip based on Ring Topologies 118
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors 116
NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators 116
Analysis of reliability/performance trade-off in Solid State Drives 116
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms 115
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation 115
Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs 115
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms 114
Designing Network On-Chip Architectures in the Nanoscale Era 114
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework 114
Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems 114
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain 114
Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer 113
The design predictability concern in optical network-on-chip design 113
Network-on-chip architectures and design methods 112
Flexible DOR Routing for Virtualization of Multicore Chips 112
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives 112
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints 112
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost 112
Process Variation and Layout Mismatch Tolerant Design of Source Synchronous Links for GALS Networks-on-Chip 112
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip 111
Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers 111
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style 110
Variation tolerant NoC design by means of self-calibrating links 110
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart 110
A Cooperative, accurate solving framework for optimal allocation, scheduling and frequency selection on energy-efficient MPSoCs 110
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming 109
Non Volatile Memory Partitioning Scheme for Technology-based Performance-Reliability Trade-off 109
Spice-Accurate SystemC Macromodels of Noisy On-Chip Communication Channels 109
Abstract Modelling of Switching Elements for Optical Networks-on-Chip with Technology Platform Awareness 109
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 109
Efficient Implementation of Distributed Routing Algorithms for NoCs 108
Bringing Network-on-Chip Links to 45nm 108
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 108
Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology 108
Network Interface Sharing Techniques for Area Optimized NoC Architectures 108
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline 108
Guided participatory research on parallel computer architectures for k-12 students through a narrative approach 108
Power efficiency of switch architecture extensions for fault tolerant NoC design 108
Application-specific power-aware workload allocation for voltage scalable MPSoC platforms 107
Communication-Aware Allocation and Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip 107
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs 106
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip 106
Power aware network interface management for streaming multimedia 105
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints 105
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. 105
Networks-on-Chip: Emerging Research Topics and Novel Ideas 104
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies 104
Energy-Reliability Trade-Off for NoCs 104
SystemC cosimulation and emulation of multiprocessor SoC designs 104
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches 104
Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology 104
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design 104
Optimizing built-in pseudo-random self-testing for network-on-chip switches 104
Energy-Efficient Multi-Processor Systems-on-Chip for Embedded Computing: Exploring Programming Models and their Architectural Support 104
Control- and Data-Path Decoupling in the Design of a NoC Switch: Area, Power and Performance Implications 103
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip 103
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing 103
PROTON+: A placement and routing tool for 3d optical networks-on-chip with a single optical layer 103
Error control schemes for on-chip communication links: the energy-reliability tradeoff 102
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. 102
A Retrospective Look at Xpipes: The Exciting Ride from a Design Experience to a Design Platform for Nanoscale Networks-on-Chip 102
Battery Lifetime Optimization for Energy-Aware Circuits 100
Variability compensation for full-swing against low-swing on-chip communication. 100
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs 100
Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip 100
Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs 99
Totale 11.622
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Categoria #
all - tutte 80.814
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 8.526
Totale 89.340
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.594 0 0 0 0 310 464 351 403 347 395 248 76
2020/20212.519 193 206 143 293 114 364 105 337 58 356 227 123
2021/20222.065 104 204 206 21 75 118 118 96 59 161 245 658
2022/20231.732 202 21 49 205 263 249 161 177 225 16 100 64
2023/2024776 90 116 49 26 59 77 40 60 5 22 17 215
2024/20251.122 104 104 345 91 478 0 0 0 0 0 0 0
Totale 17.578