Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs

There is currently a surge of interest in RRAM-based FPGAs because of their lower area, power loss resilience and their suitability for near-threshold operation. However, materializing lower dynamic and static power dissipation turns out to be challenging, since this depends on the capability of the technology to infer a large separation between RRAM resistance states. While programming strategies have been developed to achieve this, their side effects in terms of programming power overhead and lifetime of RRAM cells are typically overlooked. The justification brought by previous work consists of the typically-low number of runtime reconfigurations of FPGA devices. This paper intends to pave the way for new usage models of RRAM-based FPGAs, featuring augmented flexibility and dynamicity, thus lending themselves to emerging energy-and workload-adaptive computing systems. The paper thus captures and quantifies the fundamental correlation between programming power of RRAM cells, operational static and dynamic power of mapped designs on FPGA, and device lifetime.