Technology-Aware Communication Architecture Design for Parallel Hardware Platforms

This chapter reviews techniques for technology-aware connectivity design for the early planning of NoC architectures. On one hand, it contrasts several connectivity patterns taking the perspective of their mapping efficiency onto the 2-D silicon surface, and characterizes to which extent the theoretical properties of a topology are offset by the physical implementation trade-offs. On the other hand, it reviews a few implementation variants of the globally asynchronous locally synchronous synchronization paradigm and reviews design techniques for cost-effective and robust implementation of synchronization interfaces. Overall, this chapter describes the key steps that designers have to take to change the appealing NoC concept into mature NoC technology.