SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara

FAVALLI, Michele
 Distribuzione geografica
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Continente #
NA - Nord America 2.795
EU - Europa 564
AS - Asia 432
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 1
SA - Sud America 1
Totale 3.795
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Nazione #
US - Stati Uniti d'America 2.795
CN - Cina 271
UA - Ucraina 201
IT - Italia 101
TR - Turchia 100
DE - Germania 87
GB - Regno Unito 77
SG - Singapore 57
FI - Finlandia 49
SE - Svezia 25
FR - Francia 11
PL - Polonia 6
BE - Belgio 5
EU - Europa 2
JP - Giappone 2
RU - Federazione Russa 2
AU - Australia 1
BR - Brasile 1
ID - Indonesia 1
IN - India 1
Totale 3.795
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Città #
Woodbridge 462
Fairfield 420
Houston 263
Jacksonville 216
Ashburn 200
Seattle 172
Wilmington 157
Chandler 154
Cambridge 149
Ann Arbor 131
Izmir 84
Nanjing 76
Beijing 66
Milan 50
Princeton 45
Addison 43
Boardman 37
San Diego 32
Singapore 27
Shanghai 21
Ferrara 20
Shenyang 19
Nanchang 14
Hebei 13
Jiaxing 11
Norwalk 10
Helsinki 8
London 7
Tianjin 7
Bologna 6
Changsha 6
Jinan 6
Mountain View 6
Ningbo 6
Warsaw 6
Brussels 5
Indiana 5
Redwood City 5
Zhengzhou 5
Auburn Hills 4
Hangzhou 4
San Mateo 4
Kunming 3
New Bedfont 3
New York 3
Pensacola 3
Tappahannock 3
Verona 3
Changchun 2
Dresden 2
Falls Church 2
Haikou 2
Lanzhou 2
Los Angeles 2
Munich 2
Paris 2
Pavullo Nel Frignano 2
Prescot 2
Taizhou 2
Bagé 1
Boscoreale 1
Chicago 1
Dearborn 1
Des Moines 1
Forest City 1
Harbin 1
Hefei 1
Jakarta 1
Jinhua 1
Noci 1
Orange 1
Padova 1
Portici 1
Pune 1
San Francisco 1
San Jose 1
Shaoxing 1
Sunnyvale 1
Turin 1
Wandsworth 1
Yellow Springs 1
Totale 3.044
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Nome #
A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits 162
Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults 131
Bridging fault modeling and simulation for deep submicron CMOS ICs 112
Diversity analysis in the presence of delay faults affecting duplex systems 109
Testing Resistive Opens and Bridging Faults Through Pulse Propagation 108
A fuzzy model for path delay fault detection 107
Annotated bit flip fault model 106
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-Checking Circuits 106
A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations 103
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture 102
How many test vectors we need to detect a bridging fault? 101
Power efficiency of switch architecture extensions for fault tolerant NoC design 101
High quality test vectors for bridging faults in the presence of IC's parameters variations 101
null 99
Pulse propagation for the detection of small delay defects 97
"Victim gate" crosstalk fault model 95
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults 94
null 94
Self-checking scheme for the on-line testing of power supply noise 93
TMR voting in the presence of crosstalk faults at the voter inputs 92
null 92
Concurrent detection of power supply noise 91
Optimization of error detecting codes for the detection of crosstalk originated errors 91
Problems due to open faults in the interconnections of self-checking data-paths 88
On-Chip Clock Faults' Detector 88
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic 87
Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines 86
Modeling and Simulation of Broken Connections in CMOS ICs 86
null 84
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing 81
Regression models for behavioral power estimation 80
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices 79
Enabling testability of fault-tolerant circuits by means of I-DDQ-checkable voters 78
Symbolic handling of bridging fault effects 74
Correlation between IDDQ Testing Quality and Sensor Accuracy 64
Concurrent checking of clock signal correctness 63
Delay fault detection problems in circuits featuring a low combinational depth 62
Single Output Distribute Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures 61
Bridging Faults in Pipelined Circuits Journal of Electronic Testing, Theory and Applications 60
Test pattern generation for iddq: increasing test quality 59
null 48
A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs 23
A scalable bidimensional randomization scheme for tlc 3d nand flash memories 23
An evolutionary approach to the design of on chip pseudorandom test generators 16
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits 14
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits 13
The challenge of classification confidence estimation in dynamically-adaptive neural networks 12
Online testing approach for very deep-submicron ICs 11
Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach 8
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study 6
Totale 3.841
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Categoria #
all - tutte 15.420
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 15.420
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020970 165 38 30 141 68 107 88 101 76 72 67 17
2020/2021553 45 51 58 62 18 81 10 72 11 77 45 23
2021/2022448 12 39 40 20 14 24 33 22 8 37 47 152
2022/2023429 50 0 4 47 72 64 41 45 64 1 24 17
2023/2024184 26 22 8 6 16 11 14 12 5 3 6 55
2024/202511 11 0 0 0 0 0 0 0 0 0 0 0
Totale 3.841