statistiche ricercatore

Nome	#
Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip	211
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms	110
Flexible DOR Routing for Virtualization of Multicore Chips	108
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints	107
Efficient Implementation of Distributed Routing Algorithms for NoCs	105
Variation tolerant NoC design by means of self-calibrating links	105
Network Interface Sharing Techniques for Area Optimized NoC Architectures	103
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.	102
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints	101
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip	101
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies	100
null	98
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing	96
Yield-oriented Evaluation Methodology of Network-on-Chip Routing Implementations	92
Performance, Area and Power Breakdown Analysis for NoC Switches in 65nm Technology	75
Tight Integration of GALS Interfaces into the NoC Architecture	58
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems	16
Totale	1.688

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2019/2020	436	62	21	14	66	30	47	34	45	34	35	39	9
2020/2021	241	27	25	14	26	12	31	10	29	4	30	20	13
2021/2022	181	10	24	28	0	2	2	12	4	5	11	23	60
2022/2023	154	18	0	0	19	33	24	17	11	22	0	7	3
2023/2024	150	7	18	11	0	15	33	0	34	0	1	5	26
2024/2025	9	9	0	0	0	0	0	0	0	0	0	0	0
Totale													1.688

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