statistiche ricercatore

Nome	#
Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip	217
Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms	115
Flexible DOR Routing for Virtualization of Multicore Chips	112
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints	112
Variation tolerant NoC design by means of self-calibrating links	110
Efficient Implementation of Distributed Routing Algorithms for NoCs	108
Network Interface Sharing Techniques for Area Optimized NoC Architectures	108
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip	106
Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints	105
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.	105
Power-Optimal RTL Arithmetic-Unit Soft-Macro Selection Strategy for Leakage-Sensitive Technologies	104
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing	103
null	98
Yield-oriented Evaluation Methodology of Network-on-Chip Routing Implementations	96
Performance, Area and Power Breakdown Analysis for NoC Switches in 65nm Technology	80
Tight Integration of GALS Interfaces into the NoC Architecture	65
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems	25
Totale	1.769

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2019/2020	273	0	0	0	0	30	47	34	45	34	35	39	9
2020/2021	241	27	25	14	26	12	31	10	29	4	30	20	13
2021/2022	181	10	24	28	0	2	2	12	4	5	11	23	60
2022/2023	154	18	0	0	19	33	24	17	11	22	0	7	3
2023/2024	150	7	18	11	0	15	33	0	34	0	1	5	26
2024/2025	90	9	4	31	4	42	0	0	0	0	0	0	0
Totale													1.769

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