This poster illustrates deep integration of of the synchronizer in the switch architecture of networks-on-chip, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. The poster compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters.
Tight Integration of GALS Interfaces into the NoC Architecture
STRANO, Alessandro;MEDARDONI, Simone;BERTOZZI, Davide;
2009
Abstract
This poster illustrates deep integration of of the synchronizer in the switch architecture of networks-on-chip, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. The poster compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters.File in questo prodotto:
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