statistiche ricercatore

Continente	#
NA - Nord America	1.568
AS - Asia	794
EU - Europa	270
SA - Sud America	139
AF - Africa	14
Continente sconosciuto - Info sul continente non disponibili	13
OC - Oceania	1
Totale	2.799

Nazione	#
US - Stati Uniti d'America	1.533
SG - Singapore	290
CN - Cina	214
BR - Brasile	119
VN - Vietnam	104
UA - Ucraina	70
HK - Hong Kong	57
TR - Turchia	50
DE - Germania	43
GB - Regno Unito	33
FI - Finlandia	29
IT - Italia	28
CA - Canada	19
FR - Francia	19
IN - India	18
JP - Giappone	18
RU - Federazione Russa	17
SE - Svezia	12
BD - Bangladesh	10
IQ - Iraq	10
MX - Messico	10
ID - Indonesia	6
AR - Argentina	5
AT - Austria	5
EC - Ecuador	5
ZA - Sudafrica	5
ES - Italia	4
PL - Polonia	4
TN - Tunisia	4
CO - Colombia	3
MA - Marocco	3
SA - Arabia Saudita	3
UY - Uruguay	3
UZ - Uzbekistan	3
BE - Belgio	2
CR - Costa Rica	2
EG - Egitto	2
HN - Honduras	2
NP - Nepal	2
OM - Oman	2
VE - Venezuela	2
AE - Emirati Arabi Uniti	1
AF - Afghanistan, Repubblica islamica di	1
AL - Albania	1
AU - Australia	1
AZ - Azerbaigian	1
BO - Bolivia	1
CL - Cile	1
GT - Guatemala	1
HR - Croazia	1
IL - Israele	1
JM - Giamaica	1
KZ - Kazakistan	1
LT - Lituania	1
MY - Malesia	1
NL - Olanda	1
PH - Filippine	1
Totale	2.786

Nome	#
Cooperative built-in self-testing and self-diagnosis of NOC bisynchronous channels	226
Technology-Aware Communication Architecture Design for Parallel Hardware Platforms	222
Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture	198
Bringing Network-on-Chip Links to 45nm	196
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs	190
Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology	189
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints	189
System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic	187
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip	182
Contrasting Multi-Synchronous MPSoC Design Styles for Fine-Grained Clock Domain Partitioning: the Full-HD Video Playback Case Study	177
A library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design	146
Mesochronous NoC Technology for Power-Efficient GALS MPSoC	144
A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs	115
Topology Exploration	108
The Synchronization Challenge	100
null	99
null	89
null	42
Totale	2.799

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2021/2022	165	0	23	16	0	6	11	10	10	4	12	23	50
2022/2023	130	15	1	1	9	23	17	14	12	21	1	10	6
2023/2024	55	7	8	4	3	7	8	0	0	2	0	0	16
2024/2025	318	11	4	32	14	33	51	3	1	46	49	56	18
2025/2026	1.033	126	104	88	96	176	49	119	43	91	94	35	12
2026/2027	72	21	51	0	0	0	0	0	0	0	0	0	0
Totale													2.799

SFERA Archivio dei prodotti della Ricerca dell'Università di Ferrara