Assessing the testability of high-quality digital ICs requires consideration of the most likely physical defects and their likelihood of occurrence, thus enhancing the accuracy of test length estimates for BIST. © 1994, IEE. All rights reserved.
Realistic Testability Estimates for CMOS IC's
OLIVO, Piero;
1994
Abstract
Assessing the testability of high-quality digital ICs requires consideration of the most likely physical defects and their likelihood of occurrence, thus enhancing the accuracy of test length estimates for BIST. © 1994, IEE. All rights reserved.File in questo prodotto:
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