The paper presents an experimental analysis of DFT techniques used to detect the presence of faulty resistive paths throughout CMOS IC's. Current monitoring, delay fault testing, and new design-for-testability (DFT) techniques are compared by means of a chip designed ad hoc that allows the presence of resistive bridgings within standard functional blocks to be simulated via hardware. The results presented in this work suggest that specific DFT techniques offer considerable advantages over more conventional approaches. © 1993 IEEE
An Experimental Study of Testing Techniques for Bridging Faults in CMOS ICs
OLIVO, Piero;
1993
Abstract
The paper presents an experimental analysis of DFT techniques used to detect the presence of faulty resistive paths throughout CMOS IC's. Current monitoring, delay fault testing, and new design-for-testability (DFT) techniques are compared by means of a chip designed ad hoc that allows the presence of resistive bridgings within standard functional blocks to be simulated via hardware. The results presented in this work suggest that specific DFT techniques offer considerable advantages over more conventional approaches. © 1993 IEEEFile in questo prodotto:
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