This work presents a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for tansistor stuck-open anbd stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. © 1991 IEEE
Fault Simulation of Unconventional Faults in CMOS Circuits
OLIVO, Piero;
1991
Abstract
This work presents a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for tansistor stuck-open anbd stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. © 1991 IEEEFile in questo prodotto:
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