Resistive switching memory (RRAM) is a promising technology for embedded memory and its application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix-vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations, which might cause degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slopes in the programming characteristics. We test the accuracy of a two-layer fully connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a tradeoff between the FC-NN accuracy, size, and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.

Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits

Zambelli C.;Olivo P.;
2021

Abstract

Resistive switching memory (RRAM) is a promising technology for embedded memory and its application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix-vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations, which might cause degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slopes in the programming characteristics. We test the accuracy of a two-layer fully connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a tradeoff between the FC-NN accuracy, size, and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.
2021
Milo, V.; Glukhov, A.; Perez, E.; Zambelli, C.; Lepri, N.; Mahadevaiah, M. K.; Quesada, E. P. -B.; Olivo, P.; Wenger, C.; Ielmini, D.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2472239
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