Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge

Deploying Deep Learning (DL) models on edge devices presents several challenges due to the limited set of processing and memory resources, and the bandwidth constraints while ensuring performance and energy requirements. In-memory computing (IMC) represents an efficient way to accelerate the inference of data-intensive DL tasks on the edge. Recently, several analog, digital, and mixed digital-analog memory technologies emerged as promising solutions for IMC. Among them, digital SRAM IMC exhibits a deterministic behavior and compatibility with advanced technology scaling rules making it a viable path for integration with hardware accelerators. This work focuses on discussing the potentially powerful aspects of digital IMC (DIMC) on edge System-on-Chip (SoC) devices. The limitations and ()pen challenges of DIMC are also discussed.