Plasmonic nanoantennas integrated with silicon waveguides are a suitable solution for the implementation of on-chip wireless communications at optical frequencies. The use of optical wireless links simplifies on chip network design, mitigating switching and routing issues, while avoiding electro-optical conversion. In this work, we investigate the performance of multiple parallel on-chip optical interconnections by taking into account cross-link interference, which arises when the links reuse the same optical frequency. This analysis combines two approaches: FDTD simulation to evaluate both the radiation diagram of the antennas used in the optical links and the near-field coupling between transmit and receive neighbor antennas, and system-analysis to evaluate interference effects on link error probability. The results obtained will enable us to design the distances among parallel interconnections in order to preserve acceptable bit error probability.

On-chip optical wireless interconnections with plasmonic nanoantennas

Dehkordi, Jinous Shafiei
Primo
Conceptualization
;
Bellanca, Gaetano
Secondo
Methodology
;
Tralli, Velio
Ultimo
Methodology
2018

Abstract

Plasmonic nanoantennas integrated with silicon waveguides are a suitable solution for the implementation of on-chip wireless communications at optical frequencies. The use of optical wireless links simplifies on chip network design, mitigating switching and routing issues, while avoiding electro-optical conversion. In this work, we investigate the performance of multiple parallel on-chip optical interconnections by taking into account cross-link interference, which arises when the links reuse the same optical frequency. This analysis combines two approaches: FDTD simulation to evaluate both the radiation diagram of the antennas used in the optical links and the near-field coupling between transmit and receive neighbor antennas, and system-analysis to evaluate interference effects on link error probability. The results obtained will enable us to design the distances among parallel interconnections in order to preserve acceptable bit error probability.
2018
1450357113
978-145035711-1
Networks, Networks on Chip, Interference Analysis, On-chip communications, Plasmonic Antennas
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11392/2395444
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