In this work a SET/RESET investigation in cycling on ReRAM arrays has been performed, in order to find the most reliable SET/RESET operation conditions. The analysis will compare DC and pulsed SET/RESET operations featuring different durations and voltages on previously DC formed 1T-1R 4kbits memory arrays. A thorough analysis of the ReRAM reliability joining the cell-to-cell variability analysis to that of cycling evaluations in complete arrays is addressed. A comparison between DC and Pulse SET/RESET in terms of switching yield, read window, device-to-device uniformity and bit error rate is reported. Finally, the impact of a temperature bake at 125C on a cycled array is shown to study the temperature impact on the array variability.
Electrical characterization of read window in reram arrays under different SET/RESET cycling conditions
ZAMBELLI, Cristian;GROSSI, Alessandro;OLIVO, Piero;
2014
Abstract
In this work a SET/RESET investigation in cycling on ReRAM arrays has been performed, in order to find the most reliable SET/RESET operation conditions. The analysis will compare DC and pulsed SET/RESET operations featuring different durations and voltages on previously DC formed 1T-1R 4kbits memory arrays. A thorough analysis of the ReRAM reliability joining the cell-to-cell variability analysis to that of cycling evaluations in complete arrays is addressed. A comparison between DC and Pulse SET/RESET in terms of switching yield, read window, device-to-device uniformity and bit error rate is reported. Finally, the impact of a temperature bake at 125C on a cycled array is shown to study the temperature impact on the array variability.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
