We present a microring-based integrated router in Silicon-on-Insulator technology suitable for optical networking at chip level. The switching functionalities in a 3-channels 10 Gbit/s WDM configuration are evaluated through the BER curves. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.
Bit error rate performance evaluation of a Silicon-on-Insulator optical-network-on-chip router in a WDM configuration
PARINI, Alberto;BELLANCA, Gaetano;
2013
Abstract
We present a microring-based integrated router in Silicon-on-Insulator technology suitable for optical networking at chip level. The switching functionalities in a 3-channels 10 Gbit/s WDM configuration are evaluated through the BER curves. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.File in questo prodotto:
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