We present design and validation of a prototype of a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as a set of chaotic maps. The prototype has been implemented in AMS 0.35 um 2P3M technology and has a nominal throughput of 40 Mbits/sec. The circuit can be formally proved to deliver perfectly uncorrelated output sequences. Here we take into account the effects of implementation errors by analyzing sequences generated by the prototype, and we introduce a data post-processing methodology suitable for their compensation and for assuring robust behavior, looking for the simplest architecture that ensures a certain quality of the generated sequences.
Simple and Effective Post-Processing Stage for Random Stream Generated by a Chaos-Based RNG
PARESCHI, Fabio;SETTI, Gianluca
2006
Abstract
We present design and validation of a prototype of a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as a set of chaotic maps. The prototype has been implemented in AMS 0.35 um 2P3M technology and has a nominal throughput of 40 Mbits/sec. The circuit can be formally proved to deliver perfectly uncorrelated output sequences. Here we take into account the effects of implementation errors by analyzing sequences generated by the prototype, and we introduce a data post-processing methodology suitable for their compensation and for assuring robust behavior, looking for the simplest architecture that ensures a certain quality of the generated sequences.I documenti in SFERA sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
